Informatics, Electronics and Digital Systems, Digital Electronics, Microprocessors, Heterogeneous Systems
[Closed]
Work description
- Familiarization with the existing codebase and project objectives; - Familiarization with the x-heep platform, used for simulating RISC-V SoCs; - Continuation of the validation (potentially through simulation) and development of a custom in-house instruction set designed for controlling an external accelerator connected to the RISC-V core; - Extension of the existing RISC-V core in the x-heep platform with the instruction set to enable direct control of the accelerator by the RISC-V core; - (Optionally) Consolidation of the existing codebase for an accelerator simulator; - Collaboration in writing a scientific article to disseminate the results.
Academic Qualifications
Graduation or enrollment in a master's degree in electrical engineering, computer science, or a related field;
Minimum profile required
- Experience in HDL and C++;- Fluency in English (written and spoken).
Preference factors
Experience with RISC-V; Experience with Verilator or other co-simulation approaches; Fluent in Portuguese and English (written and spoken).
Application Period
Since 07 Dec 2024 to 19 Dec 2024
[Closed]
Centre
Telecommunications and Multimedia